Switzerland, Sept. 17 -- STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, announced new details regarding the development of the next generations of Panel-Level Packaging (PLP) technology through a pilot line in its Tours site, France, which is expected to be operational in Q3 2026.PLP is an advanced, automated chip packaging and test process technology bringing increased manufacturing efficiency and reducing costs, and a key enabler for creating the next generation of smaller, more powerful, and cost-effective electronic devices. The large-area carrier in PLP (large rectangular shapes in place of circular wafers) enables higher manufacturing throughput, making it a more ef...