US Patent Issued to WUXI ESIONTECH on Feb. 3 for "Routing node scheduling method for network on chip (NOC) in field programmable gate array (FPGA)" (Chinese Inventors)

ALEXANDRIA, Va., Feb. 3 -- United States Patent no. 12,542,748, issued on Feb. 3, was assigned to WUXI ESIONTECH Co. LTD. (Wuxi, China).

"Routing node scheduling method for network on chip (NOC) in field programmable gate array (FPGA)" was invented by Yueer Shan (Wuxi, China), Yanfeng Xu (Wuxi, China), Jicong Fan (Wuxi, China) and Zhenkai Ji (Wuxi, China).

According to the abstract* released by the U.S. Patent & Trademark Office: "A routing node scheduling method for an NOC in an FPGA is used when a plurality of input ports each have a data packet to be transmitted to a routing node at the same time. A scheduling controller within the routing node is used to enable each input port according to a predetermined scheduling order, and the rou...