US Patent Issued to Ventana Micro Systems on Oct. 21 for "Microprocessor that performs selective multi-fetch block macro-op cache entry invalidation" (California Inventors)

ALEXANDRIA, Va., Oct. 28 -- United States Patent no. 12,450,067, issued on Oct. 21, was assigned to Ventana Micro Systems Inc. (Cupertino, Calif.).

"Microprocessor that performs selective multi-fetch block macro-op cache entry invalidation" was invented by John G. Favor (San Francisco) and Michael N. Michael (Folsom, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream and a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs). An ME holds MOPs into which architectural instructions of one or more FBlks are decoded. The PRU receives a detection of a first instance in which...