US Patent Issued to Ventana Micro Systems on May 13 for "Performance and power efficient processor when switching between fetching from decoded and non-decoded instruction sources" (California Inventors)

ALEXANDRIA, Va., June 12 -- United States Patent no. 12,299,449, issued on May 13, was assigned to Ventana Micro Systems Inc. (Cupertino, Calif.).

"Performance and power efficient processor when switching between fetching from decoded and non-decoded instruction sources" was invented by John G. Favor (San Francisco) and Michael N. Michael (Folsom, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A microprocessor includes an instruction cache (IC) of architectural instructions (AIs) and a macro-op cache (MOC) comprising a MOC tag RAM (MTR) and a MOC data RAM (MDR) that holds macro-ops (MOPs) into which AIs have been translated. A MOC entry comprises one MTR entry and one or more MDR entries. A prediction...