US Patent Issued to Tokyo Electron on Oct. 7 for "Compact 3D design and connections with optimum 3D transistor stacking" (Florida, Texas Inventors)

ALEXANDRIA, Va., Oct. 8 -- United States Patent no. 12,439,641, issued on Oct. 7, was assigned to Tokyo Electron Ltd. (Tokyo).

"Compact 3D design and connections with optimum 3D transistor stacking" was invented by H. Jim Fulford (Marianna, Fla.), Mark I. Gardner (Cedar Creek, Texas) and Partha Mukhopadhyay (Oviedo, Fla.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first channel structure positioned over a substrate, first source/drain (S/D) regions positioned on ends of the first channel structure, and a first gate structure disposed all around the first channel structure. The second transistor incl...