US Patent Issued to Tokyo Electron on Oct. 14 for "Inverted top-tier FET for multi-tier gate-on-gate 3-dimension integration (3Di)" (New York, Texas Inventors)

ALEXANDRIA, Va., Oct. 21 -- United States Patent no. 12,446,291, issued on Oct. 14, was assigned to Tokyo Electron Ltd. (Tokyo).

"Inverted top-tier FET for multi-tier gate-on-gate 3-dimension integration (3Di)" was invented by Daniel Chanemougame (Albany, N.Y.), Lars Liebmann (Albany, N.Y.), Jeffrey Smith (Albany, N.Y.), Paul Gutwin (Albany, N.Y.) and Xiaoqing Xu (Austin, Texas).

According to the abstract* released by the U.S. Patent & Trademark Office: "Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first semiconductor device tier that includes first semiconductor devices. A first signal wiring structure can be formed over and electrically ...