US Patent Issued to Tokyo Electron on Dec. 23 for "Method and structures to reduce resistivity in three-dimensional structures for microelectronic workpieces using material deposited in recesses at edges of holes in a multilayer stack" (South Korean, American Inventors)

ALEXANDRIA, Va., Dec. 23 -- United States Patent no. 12,507,408, issued on Dec. 23, was assigned to Tokyo Electron Ltd. (Tokyo).

"Method and structures to reduce resistivity in three-dimensional structures for microelectronic workpieces using material deposited in recesses at edges of holes in a multilayer stack" was invented by Soo Doo Chae (Albany, N.Y.), Sang Cheol Han (Albany, N.Y.) and Youngwoo Park (Hwaseong-si, South Korea).

According to the abstract* released by the U.S. Patent & Trademark Office: "In certain embodiments, a 3D structure for a microelectronic workpiece includes a multilayer stack that includes polysilicon layers separated by other layers, holes formed within the multilayer stack, recesses formed within the polysili...