US Patent Issued to Tokyo Electron on April 29 for "3D integration of 3D NAND and vertical logic beneath memory" (New York Inventors)

ALEXANDRIA, Va., June 9 -- United States Patent no. 12,289,885, issued on April 29, was assigned to Tokyo Electron Ltd. (Tokyo).

"3D integration of 3D NAND and vertical logic beneath memory" was invented by Mark I. Gardner (Albany, N.Y.) and H. Jim Fulford (Albany, N.Y.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Three-dimensional (3D) NAND memory structures and methods to manufacture 3D NAND memory structures are disclosed. A method includes forming a stack of layers that includes a first sub-stack for a transistor structure and a second sub-stack for a memory structure positioned on the first sub-stack. The second sub-stack includes at least one layer of conductive material and at least one layer of non...