US Patent Issued to The Regents of the University of California on Nov. 11 for "CMOS-compatible graphene structures, interconnects and fabrication methods" (California Inventors)

ALEXANDRIA, Va., Nov. 11 -- United States Patent no. 12,469,748, issued on Nov. 11, was assigned to The Regents of the University of California (Oakland, Calif.).

"CMOS-compatible graphene structures, interconnects and fabrication methods" was invented by Kaustav Banerjee (Goleta, Calif.), Junkai Jiang (Sunnyvale, Calif.) and Kunjesh Agashiwala (Santa Barbara, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "An MLG (multilayer graphene) device layer structure is connected with a via. The structure includes an M1 MLG interconnect device layer upon a dielectric layer. Interlayer dielectric isolates the M1 MLG interconnect device layer. An M2 MLG interconnect device layer is upon the interlayer dielectric....