US Patent Issued to Taiwan Semiconductor Manufacturing on May 13 for "Reducing internal node loading in combination circuits" (Taiwanese Inventors)

ALEXANDRIA, Va., June 12 -- United States Patent no. 12,300,605, issued on May 13, was assigned to Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan).

"Reducing internal node loading in combination circuits" was invented by Chien-Yuan Chen (Hsinchu, Taiwan), Cheng-Hung Lee (Hsinchu, Taiwan), Hung-Jen Liao (Hsin-Chu, Taiwan), Hau-Tai Shieh (Hsinchu, Taiwan), Kao-Cheng Lin (Taipei, Taiwan) and Wei-Min Chan (Sindian, Taiwan).

According to the abstract* released by the U.S. Patent & Trademark Office: "Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transis...