US Patent Issued to TAIWAN SEMICONDUCTOR MANUFACTURING on July 15 for "Integrated circuit layout generation method" (Taiwanese Inventors)

ALEXANDRIA, Va., July 16 -- United States Patent no. 12,361,199, issued on July 15, was assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. (Hsinchu, Taiwan).

"Integrated circuit layout generation method" was invented by Ke-Ying Su (Hsinchu, Taiwan), Jon-Hsu Ho (Hsinchu, Taiwan), Ke-Wei Su (Hsinchu, Taiwan), Liang-Yi Chen (Hsinchu, Taiwan), Wen-Hsing Hsieh (Hsinchu, Taiwan), Wen-Koi Lai (Hsinchu, Taiwan), Keng-Hua Kuo (Hsinchu, Taiwan), KuoPei Lu (Hsinchu, Taiwan), Lester Chang (Hsinchu, Taiwan) and Ze-Ming Wu (Hsinchu, Taiwan).

According to the abstract* released by the U.S. Patent & Trademark Office: "A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the g...