US Patent Issued to Taiwan Semiconductor Manufacturing on July 1 for "Bottom electrode via and conductive barrier design to eliminate electrical short in memory devices" (Taiwanese Inventors)

ALEXANDRIA, Va., July 3 -- United States Patent no. 12,349,602, issued on July 1, was assigned to Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan).

"Bottom electrode via and conductive barrier design to eliminate electrical short in memory devices" was invented by Chern-Yow Hsu (Chu-Bei, Taiwan) and Shih-Chang Liu (Alian Township, Taiwan).

According to the abstract* released by the U.S. Patent & Trademark Office: "In some embodiments, the present disclosure relates to an integrated chip (IC), including a bottom electrode overlying an interconnect structure disposed within a lower inter-level dielectric (ILD) layer, a top electrode over the bottom electrode, a data storage structure between the top electrode from the bottom el...