US Patent Issued to Synopsys on Sept. 2 for "Static timing analysis of multi-die three-dimensional integrated circuits" (Oregon, California Inventors)

ALEXANDRIA, Va., Sept. 3 -- United States Patent no. 12,406,127, issued on Sept. 2, was assigned to Synopsys Inc. (Sunnyvale, Calif.).

"Static timing analysis of multi-die three-dimensional integrated circuits" was invented by Subramanyam Sripada (Portland, Ore.) and Song Chen (San Jose, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A system performs timing analysis of three-dimensional integrated circuits (3DICs). The circuit design is targeted for implementation on a stacked die that has a plurality of dies. The circuit design includes portions of the circuit design, each portion of the targeted for a different die. The system selects a net that crosses die boundaries and determines a plurality of ...