US Patent Issued to Synopsys on July 8 for "Validating test patterns ported between different levels of a hierarchical design of an integrated circuit" (French, Canadian, Italian, Indian Inventors)

ALEXANDRIA, Va., July 9 -- United States Patent no. 12,352,811, issued on July 8, was assigned to Synopsys Inc. (Sunnyvale, Calif.).

"Validating test patterns ported between different levels of a hierarchical design of an integrated circuit" was invented by Andrea Costa (Delta, Canada), Frederic Jean Neuveux (Grenoble, France), Salvatore Talluto (Gavirate, Italy), Sorin Ioan Popa (Saint-Ismier, France) and Leela Krishna Thota (Bangalore, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "A block of circuitry contains at least one sub-block. Test patterns for the sub-block (sub-level test patterns) include sub-level test stimuli and corresponding sub-level test responses. These are ported to the block-level...