US Patent Issued to Synopsys on Dec. 2 for "Performing timing constraint equivalence checking on circuit designs" (Indian, American Inventors)

ALEXANDRIA, Va., Dec. 2 -- United States Patent no. 12,488,169, issued on Dec. 2, was assigned to Synopsys Inc. (Sunnyvale, Calif.).

"Performing timing constraint equivalence checking on circuit designs" was invented by Subramanyam Sripada (Hillsboro, Ore.), Gowrishankar N. J. (Chikkamagalurur, India), Shubhashish Rudra (Bangalore, India) and Ajit Sequeira (Bengaluru, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "A first set of timing relationships may be determined in a first circuit design based on a first set of timing constraints specified for the first circuit design. A second set of timing relationships may be determined in a second circuit design based on a second set of timing constraints spec...