ALEXANDRIA, Va., June 5 -- United States Patent no. 12,277,374, issued on April 15, was assigned to Synopsys Inc. (Sunnyvale, Calif.).
"Synthesis placement bounds based on physical timing analysis" was invented by David Castle (Irvine, Calif.).
According to the abstract* released by the U.S. Patent & Trademark Office: "Embodiments provide for improved placement bounds. An example method includes identifying, based on a first synthesizing of an integrated circuit layout representation, a plurality of integrated circuit endpoints. The example method further includes identifying, based on a plurality of feature vectors each representing an endpoint of the plurality of integrated circuit endpoints, a plurality of integrated circuit clusters. ...