US Patent Issued to STMicroelectronics International on Oct. 7 for "At-speed transition fault testing for a multi-port and multi-clock memory" (Indian Inventors)

ALEXANDRIA, Va., Oct. 8 -- United States Patent no. 12,437,825, issued on Oct. 7, was assigned to STMicroelectronics International N.V. (Geneva).

"At-speed transition fault testing for a multi-port and multi-clock memory" was invented by Tanuj Kumar (Noida, India), Hitesh Chawla (Noida, India), Bhupender Singh (New Delhi), Harsh Rawat (Haryana, India), Kedar Janardan Dhori (Ghaziabad, India), Manuj Ayodhyawasi (Noida, India), Nitin Chawla (Noida, India) and Promod Kumar (Greater Noida, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port ...