US Patent Issued to STMicroelectronics International on Nov. 25 for "Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current" (Indian Inventors)

ALEXANDRIA, Va., Nov. 25 -- United States Patent no. 12,482,518, issued on Nov. 25, was assigned to STMicroelectronics International N.V. (Geneva).

"Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current" was invented by Kedar Janardan Dhori (Ghaziabad, India), Nitin Chawla (Noida, India), Promod Kumar (Greater Noida, India), Harsh Rawat (Faridabad, India) and Manuj Ayodhyawasi (Noida, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an ...