US Patent Issued to STMicroelectronics International on April 8 for "Low noise phase lock loop (PLL) circuit" (Indian Inventors)

ALEXANDRIA, Va., April 9 -- United States Patent no. 12,273,117, issued on April 8, was assigned to STMicroelectronics International N.V. (Geneva).

"Low noise phase lock loop (PLL) circuit" was invented by Anand Kumar (Noida, India) and Prashutosh Gupta (Ballia, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the ...