US Patent Issued to STMICROELECTRONICS, STMicroelectronics International on Aug. 12 for "Tagged memory operated at lower VMIN in error tolerant system" (Indian, Italian, Swiss Inventors)

ALEXANDRIA, Va., Aug. 12 -- United States Patent no. 12,386,506, issued on Aug. 12, was assigned to STMICROELECTRONICS S.r.l. (Argrate Brianza, Italy) and STMicroelectronics International N.V. (Geneva).

"Tagged memory operated at lower VMIN in error tolerant system" was invented by Nitin Chawla (Noida, India), Giuseppe Desoli (San Fermo della Battaglia, Italy), Anuj Grover (New Delhi), Thomas Boesch (Rovio, Switzerland), Surinder Pal Singh (Noida, India) and Manuj Ayodhyawasi (Noida, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plural...