US Patent Issued to SOITEC on March 25 for "Method for fabricating a strained semiconductor-on-insulator substrate" (French Inventors)

ALEXANDRIA, Va., March 26 -- United States Patent no. 12,261,079, issued on March 25, was assigned to SOITEC (Bernin, France).

"Method for fabricating a strained semiconductor-on-insulator substrate" was invented by Walter Schwarzenbach (Saint Nazaire Les Eymes, France), Guillaume Chabanne (Le Touvet, France) and Nicolas Daval (Goncelin, France).

According to the abstract* released by the U.S. Patent & Trademark Office: "A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The ...