US Patent Issued to SJ Semiconductor(Jiangyin) on Nov. 25 for "Wafer-level ASIC 3D integrated substrate, packaging device and preparation method" (Chinese Inventors)

ALEXANDRIA, Va., Nov. 25 -- United States Patent no. 12,482,759, issued on Nov. 25, was assigned to SJ Semiconductor(Jiangyin) Corp. (Jiangyin, China).

"Wafer-level ASIC 3D integrated substrate, packaging device and preparation method" was invented by Yenheng Chen (Jiangyin, China), Chengchung Lin (Jiangyin, China), Jangshen Lin (Jiangyin, China) and Mingchih Chen (Jiangyin, China).

According to the abstract* released by the U.S. Patent & Trademark Office: "The present disclosure provides a wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method. The substrate includes a first wiring layer, conductive pillars, a molding layer, a second wiring layer and solder balls. The first wiring layer includes a first die...