US Patent Issued to SJ Semiconductor(Jiangyin) on Dec. 30 for "Wafer-level ASIC 3D integrated substrate, packaging device and preparation method" (Chinese Inventors)

ALEXANDRIA, Va., Dec. 31 -- United States Patent no. 12,512,411, issued on Dec. 30, was assigned to SJ Semiconductor(Jiangyin) Corp. (Jiangyin, China).

"Wafer-level ASIC 3D integrated substrate, packaging device and preparation method" was invented by Yenheng Chen (Jiangyin, China), Chengchung Lin (Jiangyin, China), Jangshen Lin (Jiangyin, China) and Mingchih Chen (Jiangyin, China).

According to the abstract* released by the U.S. Patent & Trademark Office: "A wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method are disclosed. The substrate includes a first wiring layer conductive pillars, a molding layer, a second wiring layer, a bridge IC structure and solder balls. The first wiring layer includes a first...