US Patent Issued to Sandisk Technologies on Nov. 4 for "Select gate bias gradation structure in NAND memory" (Japanese Inventors)

ALEXANDRIA, Va., Nov. 6 -- United States Patent no. 12,461,692, issued on Nov. 4, was assigned to Sandisk Technologies Inc. (Milpitas, Calif.).

"Select gate bias gradation structure in NAND memory" was invented by Kazuki Isozumi (Kuwana, Japan) and Shinsuke Yada (Nagoya, Japan).

According to the abstract* released by the U.S. Patent & Trademark Office: "To address neighbor select gate interference between neighboring NAND block sub-divisions when one sub-division is program selected and its neighbor is un-selected, a biasing scheme for the GIDL select gates is introduced to reduce such disturbs. In a three-dimensional NAND memory with a sub-division structure and with two drain side GIDL select gate layers, when a sub-division is program ...