US Patent Issued to SAMSUNG ELECTRONICS on Nov. 18 for "Clock selection method for multiplying delay locked loop" (Indian Inventors)

ALEXANDRIA, Va., Nov. 18 -- United States Patent no. 12,476,641, issued on Nov. 18, was assigned to SAMSUNG ELECTRONICS Co. LTD. (Suwon-si, South Korea).

"Clock selection method for multiplying delay locked loop" was invented by Venkatasuryam Setty Issa (Bengaluru, India), Aswani Aditya Kumar Tadinada (Bengaluru, India) and Subba Reddy Siddamurthy (Bengaluru, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "There is provided a method for generating a select signal for a multiplexer of a Multiplying Delay Locked Loop (MDLL). The method includes determining that an output of a divider of the MDLL is a high level, determining that an output signal of a multiplexed voltage controlled oscillator (VCO) of the ...