US Patent Issued to RENESAS ELECTRONICS on Sept. 16 for "Failure analysis device and failure analysis method" (Japanese Inventors)

ALEXANDRIA, Va., Sept. 17 -- United States Patent no. 12,417,812, issued on Sept. 16, was assigned to RENESAS ELECTRONICS Corp. (Tokyo).

"Failure analysis device and failure analysis method" was invented by Toru Ogushi (Tokyo), Sho Uesugi (Tokyo) and Yukihisa Funatsu (Tokyo).

According to the abstract* released by the U.S. Patent & Trademark Office: "A failure analysis device is for analyzing a failure of the semiconductor device equipped with a logic circuit and a memory circuit. It has a storage device and a processor. The storage device stores fail bit data obtained by testing the memory circuit and failure diagnosis data obtained by failure diagnosis for test results of the logic circuit. The processor extracts the fail I/O value from...