US Patent Issued to Powerchip Semiconductor Manufacturing on Sept. 23 for "Stacked memory with a timing adjustment function" (Japanese Inventor)

ALEXANDRIA, Va., Sept. 23 -- United States Patent no. 12,424,264, issued on Sept. 23, was assigned to Powerchip Semiconductor Manufacturing Corp. (Hsinchu, Taiwan).

"Stacked memory with a timing adjustment function" was invented by Takeo Okamoto (Osaka, Japan).

According to the abstract* released by the U.S. Patent & Trademark Office: "A stacked memory with a timing adjustment function is provided, including a logic chip; a memory chip coupled to the logic chip in a face-to-face manner and including plural memory tiles; plural timing adjustment devices, respectively provided in each memory tile, wherein for each memory tile, each timing adjustment device further includes a first timing adjustment device that is configured to adjust setup ...