US Patent Issued to PANASONIC INTELLECTUAL PROPERTY MANAGEMENT on Aug. 19 for "Substrate current suppression circuit, reference voltage generation circuit, and semiconductor device" (Japanese Inventors)

ALEXANDRIA, Va., Aug. 20 -- United States Patent no. 12,393,220, issued on Aug. 19, was assigned to PANASONIC INTELLECTUAL PROPERTY MANAGEMENT Co. LTD. (Osaka, Japan).

"Substrate current suppression circuit, reference voltage generation circuit, and semiconductor device" was invented by Hiroshi Koshida (Osaka, Japan), Shinzo Koyama (Osaka, Japan), Tatsuya Kabe (Osaka, Japan) and Masaki Tamaru (Kyoto, Japan).

According to the abstract* released by the U.S. Patent & Trademark Office: "A substrate current suppression circuit includes: a fixed voltage line that supplies a fixed voltage to the collectors of the third and fourth transistors. The fixed voltage is a voltage higher than the base voltage of the third and fourth transistors when the...