US Patent Issued to Northeastern University on Jan. 13 for "Ultra-low power timing circuit with PLL locking" (Massachusetts Inventor)

ALEXANDRIA, Va., Jan. 13 -- United States Patent no. 12,525,963, issued on Jan. 13, was assigned to Northeastern University (Boston).

"Ultra-low power timing circuit with PLL locking" was invented by Aatmesh Shrivastava (Weston, Mass.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Methods, systems, and computer program products are presented herein for circuit timing using ultra-low power (ULP) timing circuit systems. A ULP timing circuit system comprises a receiver circuit, phase lock loop (PLL) circuit, crystal oscillator (XO) circuit, temperature sensing and calibration circuit, and temperature compensation circuit. The receiver circuit is configured to receive a reference clock signal. The XO circuit is ...