US Patent Issued to NANYA TECHNOLOGY on March 11 for "Semiconductor memory structure having drain stressor, source stressor and buried gate and method of manufacturing the same" (Taiwanese Inventor)

ALEXANDRIA, Va., March 12 -- United States Patent no. 12,250,832, issued on March 11, was assigned to NANYA TECHNOLOGY Corp. (New Taipei, Taiwan).

"Semiconductor memory structure having drain stressor, source stressor and buried gate and method of manufacturing the same" was invented by Cheng-Hsiang Fan (Taoyuan, Taiwan).

According to the abstract* released by the U.S. Patent & Trademark Office: "The present disclosure provides a semiconductor memory structure, including a substrate, a gate structure, a first shallow trench isolation (STI), and a second STI. The gate structure, the first STI, and a second STI are disposed in the substrate. The gate structure is buried in the substrate. The gate structure is disposed between the first STI ...