US Patent Issued to Micron Technology on Oct. 28 for "Layout of conductive vias for semiconductor device" (Japanese Inventor)

ALEXANDRIA, Va., Oct. 28 -- United States Patent no. 12,456,683, issued on Oct. 28, was assigned to Micron Technology Inc. (Boise, Idaho).

"Layout of conductive vias for semiconductor device" was invented by Kayoko Shibata (Tokyo).

According to the abstract* released by the U.S. Patent & Trademark Office: "Apparatuses of overlay measurement are disclosed. An example apparatus includes: a memory array region; a peripheral region adjacent to the memory array region; a plurality of power vias in the peripheral region that provide one or more power supply voltages; and one or more wirings in the peripheral region. The one or more wirings are disposed adjacent to the memory array region. One or more power vias of the plurality of power vias ar...