US Patent Issued to Micron Technology on Nov. 25 for "Enhanced read performance for memory data word decoding using power allocation based on error pattern detection" (Indian, American Inventors)

ALEXANDRIA, Va., Nov. 25 -- United States Patent no. 12,481,556, issued on Nov. 25, was assigned to Micron Technology Inc. (Boise, Idaho).

"Enhanced read performance for memory data word decoding using power allocation based on error pattern detection" was invented by Nitul Gohain (Karnataka, India), Jameer Mulani (Mulani, India) and Jonathan S. Parry (Boise, Idaho).

According to the abstract* released by the U.S. Patent & Trademark Office: "Methods, systems, and devices to enhance read performance for memory data word decoding using power allocation based on error pattern detection in both QLC and TLC in both QLC and TLC products are described. A plurality of data words may be processed using a first decoder engine of a decoder of a memo...