US Patent Issued to Micron Technology on Nov. 25 for "Dual cache architecture and logical-to-physical mapping for a zoned random write area feature on zone namespace memory devices" (Indian Inventors)

ALEXANDRIA, Va., Nov. 25 -- United States Patent no. 12,481,584, issued on Nov. 25, was assigned to Micron Technology Inc. (Boise, Idaho).

"Dual cache architecture and logical-to-physical mapping for a zoned random write area feature on zone namespace memory devices" was invented by Pranam Shetty (Udupi, India), Manoj Selvam (Bangalore, India) and Adarsha P (Bangalore, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "A method includes allocating random write resources to a first portion of a zone having a range of LBAs and a cache storing data of the first portion of the zone. A write command is received including an LBA. The LBA is mapped to a PBA of the cache using a first L2P table. Each of one or mor...