US Patent Issued to Micron Technology on Nov. 18 for "Error avoidance for partially programmed blocks of a memory device" (California Inventors)

ALEXANDRIA, Va., Nov. 18 -- United States Patent no. 12,475,058, issued on Nov. 18, was assigned to Micron Technology Inc. (Boise, Idaho).

"Error avoidance for partially programmed blocks of a memory device" was invented by Li-Te Chang (San Jose, Calif.), Murong Lang (San Jose, Calif.) and Zhenming Zhou (San Jose, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A block of a memory device is identified. A threshold voltage offset corresponding to a wordline associated with the block is identified based on a threshold voltage offset table. The threshold voltage offset table corresponds to at least one of: a value of a media state metric associated with the block, a wordline group of the wordline, or a di...