US Patent Issued to Micron Technology on Nov. 11 for "Fast bit erase for upper tail tightening of threshold voltage distributions" (California Inventors)

ALEXANDRIA, Va., Nov. 11 -- United States Patent no. 12,469,565, issued on Nov. 11, was assigned to Micron Technology Inc. (Boise, Idaho).

"Fast bit erase for upper tail tightening of threshold voltage distributions" was invented by Sheyang Ning (San Jose, Calif.), Lawrence Celso Miranda (San Jose, Calif.) and Tomoko Ogura Iwasaki (San Jose, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, and wordlines coupled with first and second pillars. Control logic may cause wordlines to be discharged after a program pulse is applied to selected wordline. The control logic may apply a supply vo...