US Patent Issued to Micron Technology on May 13 for "Runtime storage capacity reduction avoidance in sequentially-written memory devices" (Indian Inventors)

ALEXANDRIA, Va., June 12 -- United States Patent no. 12,299,282, issued on May 13, was assigned to Micron Technology Inc. (Boise, Idaho).

"Runtime storage capacity reduction avoidance in sequentially-written memory devices" was invented by Vinay Vijendra Kumar Lakshmi (Karnataka, India) and Vijaya Janarthanam (Karnataka, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "A system includes a memory device having a plurality of blocks. A first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory. A processing device, operatively coupled to the memory device, determines that a first block...