US Patent Issued to Micron Technology on April 8 for "Partial block read level voltage compensation to decrease read trigger rates" (California Inventors)

ALEXANDRIA, Va., April 9 -- United States Patent no. 12,272,408, issued on April 8, was assigned to Micron Technology Inc. (Boise, Idaho).

"Partial block read level voltage compensation to decrease read trigger rates" was invented by Nagendra Prasad Ganesh Rao (Folsom, Calif.), Paing Z. Htet (Union City, Calif.), Sead Zildzic Jr. (Folsom, Calif.) and Thomas Fiala (Folsom, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A memory device includes a memory array having a plurality of wordlines coupled with respective memory cells of the memory array. Control logic is operatively coupled with the memory array, the control logic to perform operations including: determining, prior to performing a read operati...