US Patent Issued to MediaTek on Nov. 25 for "Dynamic voltage stress condition optimization method and dynamic voltage stress condition optimization system capable of performing block-based dynamic voltage stress wafer testing process" (Taiwanese Inventors)

ALEXANDRIA, Va., Nov. 25 -- United States Patent no. 12,480,987, issued on Nov. 25, was assigned to MediaTek Inc. (Hsinchu, Taiwan).

"Dynamic voltage stress condition optimization method and dynamic voltage stress condition optimization system capable of performing block-based dynamic voltage stress wafer testing process" was invented by Yu-Lin Yang (Hsinchu, Taiwan), Po-Chao Tsao (Hsinchu, Taiwan), Yun-San Huang (Hsinchu, Taiwan), Chia-Chun Sun (Hsinchu, Taiwan), Chin-Wei Lin (Hsinchu, Taiwan), Tung-Hsing Lee (Hsinchu, Taiwan), Chih-Min Lin (Hsinchu, Taiwan) and Chia-Yu Yang (Hsinchu, Taiwan).

According to the abstract* released by the U.S. Patent & Trademark Office: "A dynamic voltage stress (DVS) condition optimization includes selecti...