US Patent Issued to MARVELL ASIA on Jan. 28 for "Processor data cache with shared mid-level cache and low-level cache" (Massachusetts, Washington Inventors)

ALEXANDRIA, Va., Jan. 29 -- United States Patent no. 12,210,457, issued on Jan. 28, was assigned to MARVELL ASIA PTE LTD. (Singapore).

"Processor data cache with shared mid-level cache and low-level cache" was invented by Shubhendu S. Mukherjee (Southborough, Mass.), David H. Asher (Sutton, Mass.), Richard E. Kessler (Northborough, Mass.) and Srilatha Manne (Seattle).

According to the abstract* released by the U.S. Patent & Trademark Office: "A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for mul...