US Patent Issued to Kepler Computing on Aug. 5 for "Asynchronous full-adder with majority or minority gates to generate sum false output" (Oregon, Georgia, Texas, North Carolina Inventors)

ALEXANDRIA, Va., Aug. 6 -- United States Patent no. 12,379,898, issued on Aug. 5, was assigned to Kepler Computing Inc. (San Francisco).

"Asynchronous full-adder with majority or minority gates to generate sum false output" was invented by Nabil Imam (Atlanta), Amrita Mathuriya (Portland, Ore.), Ikenna Odinaka (Durham, N.C.), Rafael Rios (Austin, Texas), Rajeev Kumar Dokania (Beaverton, Ore.) and Sasikanth Manipatruni (Portland, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Asynchronous full-adder circuit is described. The full-adder includes majority and/or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledge...