US Patent Issued to Intel on Sept. 9 for "Method to reduce register access latency in split-die SoC designs" (California, Oregon, Texas, Arizona Inventors)

ALEXANDRIA, Va., Sept. 10 -- United States Patent no. 12,411,689, issued on Sept. 9, was assigned to Intel Corp. (Santa Clara, Calif.).

"Method to reduce register access latency in split-die SoC designs" was invented by Anand K. Enamandram (Folsom, Calif.), Eswaramoorthi Nallusamy (Cedar Park, Texas), Ramamurthy Krithivas (Chandler, Ariz.), Cheng-Wein Lin (Portland, Ore.) and Irene Johansen (Portland, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Methods and apparatus to reduce register access latency in split-die SoC designs. The method is implemented on a platform including a legacy socket and one or more non-legacy (NL) sockets comprising split-die System-on-Chips (SoC)s including multiple dielets i...