US Patent Issued to Intel on Sept. 9 for "Formation of gate spacers for strained PMOS gate-all-around transistor structures" (Oregon Inventors)

ALEXANDRIA, Va., Sept. 10 -- United States Patent no. 12,414,339, issued on Sept. 9, was assigned to Intel Corp. (Santa Clara, Calif.).

"Formation of gate spacers for strained PMOS gate-all-around transistor structures" was invented by Ashish Agrawal (Hillsboro, Ore.), Gilbert Dewey (Beaverton, Ore.), Siddharth Chouksey (Portland, Ore.), Jack T. Kavalieros (Portland, Ore.) and Cheng-Ying Huang (Hillsboro, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A gate-all-around transistor device includes a body including a semiconductor material, and a gate structure at least in part wrapped around the body. The gate structure includes a gate electrode and a gate dielectric between the body and the gate electrod...