US Patent Issued to Intel on Sept. 30 for "Transistor gate trench engineering to decrease capacitance and resistance" (Oregon Inventors)

ALEXANDRIA, Va., Sept. 30 -- United States Patent no. 12,433,007, issued on Sept. 30, was assigned to Intel Corp. (Santa Clara, Calif.).

"Transistor gate trench engineering to decrease capacitance and resistance" was invented by Seung Hoon Sung (Portland, Ore.), Willy Rachmady (Beaverton, Ore.), Jack T. Kavalieros (Portland, Ore.), Han Wui Then (Portland, Ore.) and Marko Radosavljevic (Portland, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-sour...