US Patent Issued to Intel on Sept. 30 for "Interlayer dielectric stack optimization for wafer bow reduction" (Oregon, California Inventors)

ALEXANDRIA, Va., Sept. 30 -- United States Patent no. 12,431,441, issued on Sept. 30, was assigned to Intel Corp. (Santa Clara, Calif.).

"Interlayer dielectric stack optimization for wafer bow reduction" was invented by Gwang-Soo Kim (Portland, Ore.), Dimitrios Antartis (Hillsboro, Ore.), Han Ju Lee (Santa Clara, Calif.) and Christopher Pelto (Beaverton, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "An integrated circuit (IC) die comprises a first metallization layer comprising first interconnect structures which each extend through the first metallization layer, a second metallization layer comprising second interconnect structures which each extend through the second metallization layer, an interlaye...