US Patent Issued to Intel on Oct. 7 for "Stacked semiconductor die architecture with multiple layers of disaggregation" (Oregon Inventor)

ALEXANDRIA, Va., Oct. 8 -- United States Patent no. 12,438,123, issued on Oct. 7, was assigned to Intel Corp. (Santa Clara, Calif.).

"Stacked semiconductor die architecture with multiple layers of disaggregation" was invented by Edward Burton (Hillsboro, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a ca...