US Patent Issued to Intel on Nov. 11 for "Gate-to-gate isolation for stacked transistor architecture via non-selective dielectric deposition structure" (Oregon Inventors)

ALEXANDRIA, Va., Nov. 11 -- United States Patent no. 12,471,363, issued on Nov. 11, was assigned to Intel Corp. (Santa Clara, Calif.).

"Gate-to-gate isolation for stacked transistor architecture via non-selective dielectric deposition structure" was invented by Nicole K. Thomas (Portland, Ore.) and Marko Radosavljevic (Portland, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. T...