ALEXANDRIA, Va., June 17 -- United States Patent no. 12,316,446, issued on May 27, was assigned to Intel Corp. (Santa Clara, Calif.).
"Latency optimization in partial width link states" was invented by Debendra Das Sharma (Saratoga, Calif.).
According to the abstract* released by the U.S. Patent & Trademark Office: "A first flit is generated according to a first flit format, where a first number of error detection codes are to be provided for an amount of data to be sent in the first flit, and the first flit is to be sent on a link by the transmitter while the link operates with a first link width. The link transitions from a first link width to a second link width, where the second link width is narrower than the first link width. A seco...