US Patent Issued to Intel on March 18 for "Multi-deck non-volatile memory architecture with reduced termination tile area" (Idaho Inventor)

ALEXANDRIA, Va., March 19 -- United States Patent no. 12,254,946, issued on March 18, was assigned to Intel Corp. (Santa Clara, Calif.).

"Multi-deck non-volatile memory architecture with reduced termination tile area" was invented by William K. Waller (Boise, Idaho).

According to the abstract* released by the U.S. Patent & Trademark Office: "In one embodiment, a non-volatile memory apparatus includes memory tiles comprising a set of main memory tiles in rows and columns, a set of row termination tiles at the ends of the rows, and a set of column termination tiles at the ends of the columns. Each memory tile includes a plurality of decks, with each deck comprising bitlines, wordlines orthogonal to the bitlines, and memory cells between ove...