US Patent Issued to Intel on March 18 for "Hierarchical hybrid network on chip architecture for compute-in-memory probabilistic machine learning accelerator" (Oregon Inventors)

ALEXANDRIA, Va., March 19 -- United States Patent no. 12,254,399, issued on March 18, was assigned to Intel Corp. (Santa Clara, Calif.).

"Hierarchical hybrid network on chip architecture for compute-in-memory probabilistic machine learning accelerator" was invented by Deepak Dasalukunte (Beaverton, Ore.), Richard Dorrance (Hillsboro, Ore.) and Hechen Wang (Hillsboro, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Systems, methods, apparatuses, and computer-readable media. An analog router of a first supertile of a plurality of supertiles of a network on a chip (NoC) may receive a first analog output from a first compute-in-memory tile of a plurality of compute-in-memory tiles of the first supertile. The...