US Patent Issued to Intel on June 17 for "Multi-stage cache tag with first stage tag size reduction" (Massachusetts Inventors)

ALEXANDRIA, Va., June 19 -- United States Patent no. 12,332,802, issued on June 17, was assigned to Intel Corp. (Santa Clara, Calif.).

"Multi-stage cache tag with first stage tag size reduction" was invented by Kermin ChoFleming (Hudson, Mass.), Yu Bai (Shrewsbury, Mass.) and Ping Zou (Westborough, Mass.).

According to the abstract* released by the U.S. Patent & Trademark Office: "An embodiment of an integrated circuit comprises circuitry to generate a cache tag for data to be stored in a cache memory, store a first portion of the cache tag in a primary tag memory, and store a second portion of the cache tag in a secondary tag memory, wherein a size of the first portion is smaller than a size of the second portion. Other embodiments are d...